ID:17907 When in systolic mode and the second pipeline register is used for DSP block WYSIWYG primitive "<atom name>", second_pipeline_clock and input_systolic_clock must share the same clock source.

CAUSE: You have set operation_mode to m18x18_systolic and used the second pipeline register (parameter second_pipeline_clock is not set to none) for the specified DSP block WYSIWYG primitive but the second pipeline clock and the input systolic clock source are different. Parameters second_pipeline_clock and input_systolic_clock should have the same value.

ACTION: Assign the same value for second_pipeline_clock and input_systolic_clock.