ID:15470 SERDES receiver or transmitter atom "<name>" has clock input port that must be driven by clk0 or clk1 output port of fast PLL

CAUSE: The specified SERDES receiver or transmitter atom has a clock input port that can be driven only by clk0 or clk1 port of a fast PLL. This error usually occurs when you instantiate a megafunction directly in an HDL file rather than using the MegaWizard Plug-In Manager .

ACTION: Modify the design so that the clock input port of the SERDES receiver or transmitter atom has a valid source.