ID:15984 The phaseinvertctrl input of I/O clock divider primitive "<name>" can only be driven by resyncinputphaseinvert output of a DQS configuration primitive

CAUSE: The phaseinvertctrl input of the specified I/O clock divider primitive has an illegal connection.

ACTION: Check the design and make sure that if the specified phaseinvertctrl input is not disconnected, it is driven by the resyncinputphaseinvert output of a DQS configuration primitive.