ID:16598 All first-stage pipeline registers must share the same clock source for DSP block WYSIWYG primitive "<name>". Change your design so the first-stage pipeline registers feeding the DSP block WYSIWYG primitive share the same clock source.

CAUSE: The first-stage pipeline registers in your design do not share the same clock source for the specified DSP block WYSIWYG primitive, however all first-stage pipeline registers must share the same clock source.

ACTION: Change your design so the first-stage pipeline register feeding the DSP block WYSIWYG primitive share the same clock source.