ID:12499 Input clock of PLL <name>, which drives at least one non-DPA mode SERDES, must be driven by a dedicated clock pin of the PLL.

CAUSE: The Fitter tried to place the specified PLL. However, the PLL drives at least one non-DPA mode SERDES. As a result, the PLL input clock must be driven by a dedicated clock pin of the PLL.

ACTION: Modify the design so that the PLL input clock is driven by a dedicated clock pin of the PLL.