ID:21203 Can't find the legal settings for PLL node "<name>" with reference clock frequency "<name>" and output clock frequency "<name>" because ES silicon LC 14G VCO is not currently supported.
CAUSE: The Quartus Prime software cannot find the legal settings for the specified PLL with the specified reference clock frequency and output clock frequency with ES silicon.
ACTION: Specify a legal set of reference clock frequency and output clock frequency such that the 14G VCO is not required to be engaged.