ID:15687 <name> input port of Clock Delay Control Calibration block "<name>" is not sourced from the clock output port of a PLL. Source this port from the clock output port of a PLL

CAUSE: The specified input port of Clock Delay Control Calibration block is not sourced from the clock output port of a PLL. This input port must be sourced from the clock output port of a PLL.

ACTION: Modify the design to source this port from the clock output port of a PLL.