ID:14066 WYSIWYG MCELL primitive "<name>" cannot use both clk and pclk ports

CAUSE: The specified WYSIWYG MCELL primitive uses both the clk and pclk ports; however, it can use only one of the two ports.

ACTION: If you are using an EDA tool, contact the technical support for the EDA tool regarding this message. For further assistance, contact Intel Technical Support by creating a Service Request at www.altera.com/mysupport.