Verilog HDL Synthesis Support

Parent topic: Verilog HDL Synthesis Support

Section 8—User Defined Primitives

Section	Construct	Intel^® Quartus^® Prime Support
8.2	Combinational UDPs	Supported
8.3	Level-Sensitive Sequential UDPs	Supported
8.4	Edge-Sensitive Sequential UDPs	Supported

Parent topic: Verilog HDL Synthesis Support

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