Setting Up Device-Wide Signals in VHDL for ModelSim^® - Intel^® FPGA Edition

To set up the VHDL Output File (.vho) Definition that contains device-wide reset or device power up signals, type the following commands in the ModelSim software main window before starting simulation:

force /< design >/< entity >/<device power up> 0 0 ns    
force /< design >/< entity >/<device power up> 1 <time> ns 
force /< design >/< entity >/<device-wide reset> 1 0 ns

Note: The variable <device-wide reset> is the name of the device-wide reset signal, <device power up> is the name of the device power up signal, and <time> is a time value between 0 and the actual starting time of the simulation.

Setting Up Device-Wide Signals in VHDL for ModelSim® - Intel® FPGA Edition

Setting Up Device-Wide Signals in VHDL for ModelSim^® - Intel^® FPGA Edition