Start Test Bench Template Writer Command (Processing Menu)

Click Processing > Start > Start EDA Test Bench Template Writer.

Allows you to generate a template for a test bench file that contains an instantiation of the top-level design entity, for simulation with other EDA tools. The test bench file is placed in the location specified as the Output directory in the Simulation page under EDA Tool Settings. The default directory is /<project directory>/simulation/<EDA simulation tool> .

Note: If you use this command after the design source files include changes from compilation, the Intel^® Quartus^® Prime software generates the test bench file with the data from the last compilation.

For more information about testbench generation, refer to the Introduction to Intel FPGA IP Cores.