TMC-20017: Loops Detected

Verify whether strongly connected components (logical loops) exist in the design netlist. These loops prevent proper timing analysis.

Recommendation

Remove the loops for your design.

Severity

High

Stage

Finalize

Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10