CLK-30031: Input Delay Assigned to Clock

Design Assistant detected an input delay constraint assigned to a clock.

Recommendation

Verify that no input delay value is set for any clock. The Compiler ignores input delays set on clock ports because clock-as-data analysis takes precedence. Remove the input delay constraint from any clock.

Severity

High

Stage

Final

Device Family

• Intel^® Agilex™
• Intel^® Stratix^® 10
• Intel^® Arria^® 10
• Intel^® Cyclone^® 10 GX