Create Timing Netlist Dialog Box (Timing Analyzer)

You open this dialog box by clicking Netlist > Create Timing Netlist in the Timing Analyzer.

Allows you to configure and load the timing netlist that the Timing Analyzer uses to calculate path delay data. Youmust create the timing netlist for each design before running the Timing Analyzer. You can use this dialog box instead of the Create Timing Netlist command in the Tasks pane if you want to specify a different speed grade or a different timing model. The command also generates Advanced I/O Timing reports for supported device (Cyclone® III, Stratix®III, and Stratix® IV) families if you turned on Enable Advanced I/O Timing in the Timing Analyzer page of the Settings: dialog box.

The following diagram shows how the Timing Analyzer interprets and classifies timing netlist data for a sample design.

Note: The timing netlist created is based on the initial configuration of the design. Any configuration changes done by the design after the device enters user mode, for example, dynamic transceiver reconfiguration, are not reflected in the timing netlist. This applies to all device families except transceivers on Intel® Arria® 10 devices with the Multiple Reconfiguration Profiles feature.


Specifies the Fitter stage snapshot for timing analysis. To evaluate timing at specific stages of the Fitter, select the planned, early placed, placed, routed, or final snapshot. These snapshot are only available after the Compiler generates the snapshot during the related Compiler stage..

Delay model:

Specifies the delay model the Timing Analyzer uses when performing timing analysis. You can make the following settings:

  • Slow-corner— Uses the worst-case (slowest) timing model to compute delays depending on the speed grade of the device specified in the Speed grade list.

    Scripting Information

    Keyword: create_timing_netlist

    Settings: -modelslow


  • Fast-corner— Uses the best-case (fastest) timing model to compute delays.
    Scripting Information

    Keyword: create_timing_netlist

    Settings: -modelfast

  • Zero IC delays— Computes timing with no interconnection delays. Use this option early in your design process to determine if your design can meet timing requirements. You can use this option with either delay model.
    Scripting Information

    Keyword: create_timing_netlist

    Settings: -zero_ic_delays

Tcl command:

Displays and allows you to enter Tcl commands for the options you specify in this dialog box.