Update Timing Netlist Command (Timing Analyzer)

Updates the timing netlist and assignment database to include newly added clocks, constraints, and exceptions. This command creates and initializes all clocks in the design, creates groups out of all point-to-point assignments, and performs all other one-time processing tasks needed for efficient analysis of the timing netlist. You must run this command before generating reports to view the effect of new timing assignments.

Before using this command, consider the following:

• If you did not define any clocks with the create_clock Synopsys^® Design Constraints (SDC) command or Create Clock dialog box, the Timing Analyzer automatically runs the derive_clocks -period 1.000 command. The derive_clocks-period1.000 command creates a 1 GHz clock on enough clock sources (top-level I/O ports or ripple clock registers) to fully constrain all core paths. This 1 GHz clock will produce timing failures, requiring you to add real clock constraints.
• If PLLs exist in the design and you did not define any clocks using the create_clock SDC command or Create Clock dialog box or any generated clocks using the create_generated_clock SDC command or Create Generated Clock dialog box, the Timing Analyzer automatically runs the derive_pll_clocks command to constrain the PLLs.