RES-30006: Combinational Logic Used as a Reset Signal is not Synchronized

Combinational logic that is used as a reset signal should be synchronized in a design. Glitches in unsynchronized combinational logic that is used as a reset signal can cause the unintentional resetting of the logic's destination register(s).

The following image shows an example of combinational logic that is used as a reset:

Figure 1. Example of Combinational Logic That is Used as a Reset

Recommendation

Combinational logic should drive a register before driving one or more input reset ports of other registers.

Important: Synchronizing the combinational logic that is used as a reset signal delays the resulting reset signal by an extra clock cycle. This delay should be considered when using the reset signal in a design.

The following image shows an example of correctly synchronized combinational logic-driven reset:

Figure 2. Example of a Correctly Synchronized Combinational Logic-Driven Reset

Severity

High

Stage

Analysis and Elaboration

Device Family

  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10