FLP-40002: Very Small Routing Regions

Very small routing regions fragment the floorplan and may not be able to fit the required logic.

This condition may lead to sub-optimal placement and routing of the design as well as an increased compilation runtime. The region must span (in horizontal and vertical directions) at least the number of units specified in the min_dimension parameter. For regions comprising more than one rectangle, the bounding box is measured.

Parameter

Name Default Value Description
min_dimension 4

Reports a violation for Logic Lock regions that have a dimension smaller than the value specified in this parameter.

Recommendation

Ensure that the region size is large enough to contain the required logic, or consider switching to location assignments if constraining a very targeted and smaller amount of logic.

Severity

Low

Stage

  • Synthesis
  • Plan
  • Place
  • Finalize

Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX