CDC-50003: CE-Type CDC No Constraints

There is no skew constraint on the data signals fed into registers that a clock enable signal controls.

Recommendation

To ensure that all bits of a multi-bit data latch on the same clock cycle while crossing clock domains, consider adding a set_max_skew constraint on the signals feeding the register data ports.

Severity

High

Stage

Plan, Finalize

Device Family

  • Intel® Stratix® 10
  • Intel® Agilex™
  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10