ACD-30024: Multiple Data Bits That are Transferred Across Asynchronous
Clock Domains are Synchronized But Not All Bits May Be Aligned
In a design, all data bits that belong to multiple-bit data and that are
transferred between asynchronous clock domains are synchronized. However, not all data
bits may be aligned in the receiving clock domain. Propagation delays may cause skew
when data reaches the receiving clock domain.
The following image shows an example of synchronized data bits
that belong to multiple-bit data and that are transferred between
asynchronous clock domains:
Figure 1. Synchronized Data Bits Example
A violation is also reported if a bus transmits partial data bits across
a clock domain.
Note: If all data bits belong to
single-bit data, the synchronization of data bits does not cause problems in the
design.
Recommendation
Consider the following:
If data bits belong to multiple-bit data, you should use a handshake
protocol to guarantee that all bits of the data bus are stable when the receiving
clock domain samples the bus.
If you use a handshake protocol, then you should synchronize only
those data bits that act as REQ (Request) and ACK (Acknowledge) signals. You need not synchronize data
bits that belong to multiple-bit data. You can ignore the violation on data bits that
use a handshake protocol.
The following image illustrates an
example of the transfer of data bits between asynchronous clock domains where only
REQ and ACK
signals are synchronized:
Figure 2. Transfer of Data Bits Between Asynchronous Clock Domains
Example