ID:150024 File with the same name as the VHDL or Verilog Design File already exists. Do you want to overwrite the file?

CAUSE: You directed the Quartus Prime software to generate a Block Design File (.bdf). However, the Quartus Prime software cannot generate the file because it has the same name as an existing VHDL Design File or Verilog Design File.

ACTION: Click Yes to close the message dialog box and overwrite the existing file, or click No and then delete or rename the existing design file, and create the new VHDL or Verilog Design File again.