ID:10541 VHDL Signal Declaration warning at <location>: used implicit default value for signal "<name>" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.

CAUSE: In a VHDL Design File (.vhd) at the specified location, you declared the specified signal, which you later used in an expression or on the right-hand side (RHS) of an assignment. However, you never assigned a value to the signal with a Concurrent Signal Assignment Statement or Sequential Signal Assignment Statement, and you did not specify an explicit default value for the signal in a Signal Declaration. As a result, Quartus Prime Integrated Synthesis used an implicit default value for the signal based on the signal's type or subtype. For example, the implicit default value for a signal with scalar type T is T'LEFT, or the left-most value in the range of T. The implicit default value for a signal with type STD_LOGIC is U, which Quartus Prime Integrated Synthesis treats as X, a Don't Care value. (Note: Quartus Prime Integrated Synthesis does not generally treat X as a Don't Care value in VHDL). The implicit default value for a signal with composite type is formed by assigning the correct implicit default value to each of the signal's subelements. The use of a implicit default values may result in unintended design optimizations.

ACTION: If you intended to use an implicit default value for the signal, no action is required. Otherwise, assign a value to the signal before using the signal in expressions or on the RHS of assignments, or specify an explicit default value in the Signal Declaration for the signal.