ID:10543 VHDL Variable Declaration warning at <location>: used default initial value for variable "<name>" because variable was never assigned a value or an initial value expression. Use of default initial value may introduce unintended design optimizations.

CAUSE: In a VHDL Design File (.vhd) at the specified location, you declared the specified variable, which you later used in an expression or on the right-hand side (RHS) of an assignment. However, you never assigned a value to the variable with a Variable Assignment Statement, and you did not specify an initial value expression for the variable in a Variable Declaration. As a result, Quartus Prime Integrated Synthesis used a default initial value for the variable based on the variable's subtype. For example, the default initial value for a variable with scalar type T is T'LEFT, or the left-most value in the range of T. The default initial value for a variable with type STD_LOGIC is X, which corresponds to STD_LOGIC'LEFT (Quartus Prime Integrated Synthesis does not treat X as a Don't Care value.) The default initial value for a variable with composite type is formed by assigning the appropriate default initial value to each of the variable's subelements. The use of a default initial value may result in unintended design optimizations.

ACTION: If you intended to use a default initial value for the variable, no action is required. Otherwise, assign a value to the variable before using the signal in expressions or on the RHS of assignments, or specify an initial value expression in the Variable Declaration for the variable.