ID:10645 VHDL type inferencing warning at <location>: two visible identifiers match "<identifier>" because the actual at position <number> has an ambiguous type - it could be "<type>" or "<type>", assuming "<type>"

CAUSE: In an expression in a VHDL Design File (.vhd) at the specified location, you used the specified name, which refers to an overloaded operator or subprogram. However, Quartus Prime Integrated Synthesis could not match the name to a unique operator or subprogram because the argument at the specified location has two possible types. To resolve the ambiguity, Quartus Prime Integrated Synthesis arbitrarily chose one of the two types for the ambiguous argument, which may or may not match the behavior you intended. For example, in the following VHDL code fragment, the literal argument to to_std_ulogicvector(X"49) could have type bit_vector or type std_logic_vector:

constant abc  : std_ulogic_vector(7 downto 0) := to_stdulogicvector(X"49");