ID:10639 VHDL warning at <location>: constant value overflow

CAUSE: At the specified location in a VHDL Design File (.vhd), you used a constant literal or an expression involving constant literals that resulted in overflow. That is, the result will not fit within the precision used to represent the value during Quartus Prime Integrated Synthesis. For example, the expression 2**50 or the integer literal 10000000000 both require more than 32 bits, which is the default internal precision used to represent integral constants in Quartus Prime Integrated Synthesis.

ACTION: Change the expression or literal to fit the restrictions of the data type.