ID:10103 Verilog HDL Module Instantiation warning at <location>: instantiated undefined module "<name>"

CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v) you attempted to instantiate the specified module, but the module is undefined. This message may occur if you do not include the design file that defines the module.

ACTION: No action is required. To avoid receiving this message in the future, make sure you include the design file that defines the module.