ID:10169 Verilog HDL warning at <location>: the port and data declarations for array port "<name>" do not specify the same range for each dimension

CAUSE: In a Verilog Design File (.v) at the specified location, you declared the specified array port using separate data and port declarations. In addition, both declarations contain ranges for the array bounds. However, the port and data declarations do not specify the same bounds for each array dimension. The Quartus Prime software will use the ranges specified by the data declaration and not the port declaration. Third-party tools may issue an error for this design.

ACTION: No action is required. To avoid receiving this message in the future, make sure the port and data declaration are consistent. Consider using Verilog-2001 style declarations to declare the direction and data type in a single declarations.