ID:10886 Verilog HDL macro warning at <location>: overriding existing definition for macro "<name>", which was defined in the Quartus Prime Settings File (.qsf) or on the command line

CAUSE: In a Verilog Design File (.v), you redefined the specified macro. The remainder of the design uses the new macro definition until you redefine the macro again.

ACTION: No action is required. To prevent this warning in the future, use a different macro name for each new definition. Using a different macro name often results in a clearer, more robust design.