ID:10846 Verilog HDL Instantiation warning at <location>: instance has no name

CAUSE: In an instantiation at the specified location in a Verilog Design File (.v), you instantiated an a module, primitive, or interface. However, you did not specify a name for your instance. In Verilog HDL, instance names are optional for gates and primitives, but not for modules or interfaces. Although Quartus Prime Integrated Synthesis does not enforce this rule, other tools such as simulators may enforce the rule more strictly and issue an error when processing your design. In addition, having no name on your instance may make it harder to locate in the synthesized netlist.

ACTION: No action is required. To remove the warning, give your instance a name.