ID:10235 Verilog HDL Always Construct warning at <location>: variable "<name>" is read inside the Always Construct but isn't in the Always Construct's Event Control

CAUSE: In an Always Construct at the specified location in a Verilog Design File (.v), you read the value of the specified variable. However, you did not include the variable in the Always Construct's Event Control (sensitivity list). Although this omission does not affect the logic generated by Quartus Prime Integrated Synthesis, it may cause the design's simulated behavior to differ from the behavior of the synthesized logic. For example, in the following code, the Always Construct reads variables a, b, and c, but the Always Construct's Event Control is sensitive only to a and b (that is, the Event Control is not sensitive to c):

               
reg [2:0] a, b, c;
reg [3:0] o;
 
               
always@(a or b) begin
   o <= a + b + c;
end

            

During simulation, o behaves as a pseudo-latch because changes to the value of c do not trigger evaluation of the Always Construct. However, Quartus Prime Integrated Synthesis ignores the pseudo-latch behavior of o by treating the Always Construct as if its Event Control were sensitive to c, and therefore implements purely combinational logic for o.