ID:10873 Using initial value X (don't care) for net "<string>" at <location>

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you declared an object that is represented by the specified net. However, you did not update the value of the net in your design. As a result, Quartus Prime Integrated Synthesis has assigned the net to its initial value, which was either X or an equivalent metalogical value. Using X as an initial value for a net may trigger unintended or undesirable design optimizations, and it's possible that the behavior of your synthesized design may not match its simulated behavior. The initial value may have come from an implicit default or initial value for a VHDL signal or variable. For example, the following VHDL fragment declares two signals: data and foo. Signal foo has two bits, but only foo(1) was assigned a value. However, foo was declared with an explicit default value. As a result, Quartus Prime Integrated Synthesis will tie foo(0) to 1.

signal data : std_logic;                           -- no default value 
signal foo : std_logic_vector(1 downto 0) := "01"; -- default value

               
foo(1) <= data;

In contrast, signal data (a scalar) has no assignment and no explicitly declared default value. Quartus Prime Integrated Synthesis will tie the net representing data to an implicit default value based on the signal's type. The implicit default value for a signal with scalar type T is T'LEFT, or the left-most value in the range of T. The implicit default value for a signal with type STD_LOGIC is U, a metalogical value which Quartus Prime Integrated Synthesis considers equivalent to X, a Don't Care value. (NOTE: Quartus Prime Integrated Synthesis does not generally treat X as a Don't Care during VHDL synthesis).