ID:10033 Reduced output of register "<text>" with <name> to <VCC or GND> at <location>

CAUSE: In the current design, the specified input signal of the specified register is stuck at VCC or GND ; that is, the register has a constant data input (data_in), a stuck asynchronous clear (aclr), or a stuck asynchronous set (aset). As a result, Quartus Prime Integrated Synthesis reduced the register output to VCC (if the input signal is stuck at VCC) or GND (if the input signal is stuck at GND).

ACTION: If you intended the register to behave in this manner, no action is required. Otherwise, check the design file for errors to make sure that the design's logic is not reduced to VCC or GND.