ID:10665 Bidirectional port "<name>" at <location> has a one-way connection to bidirectional port "<name>"

CAUSE: In a Verilog Design File (.v) or a VHDL Design File (.vhd), you declared the specified bidirectional port. Later, you assigned this bidirectional port to another bidirectional port using a directional assignment. Because the assignment is directional, data only flows one-way, that is, from the right-hand side of the assignment to the left-hand side. For example, the following VHDL fragment assigns bidirectional port b2 to the bidirectional port b1. During simulation, a change in the value of b2 will propagate to b1, but not vice-versa.

ENTITY example IS
   PORT
   (
      b1 : INOUT   BIT;
      b2 : INOUT   BIT
   );
END example;

               
ARCHITECTURE a OF example IS
BEGIN
   b2 <= b1;
 END a;

A directional assignment between bidirectional ports often represents an attempt to create a bidirectional connection between the two ports.