ID:10030 Net "<name>" at <location> has no driver or initial value, using a default initial value '<character>'

CAUSE: In a Verilog Design File (.v), you declared an object that is represented in the synthesized netlist by the specified net. However, you did not assign a value to the net or indicate its initial value using an initial construct or variable declaration assignment. As a result, Quartus Prime Integrated Synthesis tied the net to the specified default initial value, which may cause the functionality of the synthesized netlist to differ from the simulated behavior of your design. For example, in the following Verilog fragment, the variable undriven was used on the right-hand side of an assignment but was never assigned a value. Integrated Synthesis will tie undriven to a default initial value.

reg undriven;

               
assign o = undriven;

            

ACTION: No action is required. If you want to remove the warning , assign a value to the specified net or indicate its initial value with an initial construct or variable declaration assignment. In the previous example, you can force an initial value of VCC by assigning the variable undriven inside an initial construct:

initial
begin	undriven = 1'b1;
end