ID:10021 Ignored <name> synthesis attribute for port "<name>" because the synthesis attribute's pin assignment list contains <number> assignment(s), which does not match port width of <number> bit(s)
CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you attempted to specify pin assignments for the elements of the specified port using the chip_pin or altera_chip_pin_lc synthesis attribute. However, the pin assignment list for the synthesis attribute contains the specified number of pin assignments, which is too few or too many pin assignments for the port. The number of pin assignments must match the specified bit width of the port. As a result, Quartus Prime Integrated Synthesis ignored the synthesis attribute.
ACTION: Make sure you declared the port with the correct width, and check the synthesis attribute's pin assignment list for errors (for example, make sure the entries in the pin assignment list are separated by commas). To avoid specifying a location for a particular bit in a multi-bit port, leave the bit's corresponding entry in the pin assignment list blank. For example, in the following Verilog HDL code, a pin assignment list assigns a[2] and a[0] to valid pin locations, but leaves a[1] unassigned:
(* chip_pin = "1, , 2" *) input [2:0] a;
In the following VHDL code, where a is declared as unsigned(2 downto 0) in the corresponding Port Declaration, a pin assignment list assigns a[2] and a[0] to valid pin locations, but leaves a[1] unassigned:
attribute chip_pin : string; attribute chip_pin of a : signal is "1, , 2";