ID:10270 Verilog HDL Case Statement warning at <location>: incomplete case statement has no default case item

CAUSE: In a Verilog Design File (.v), you used a Case Statement. However, your case items do not cover all possible binary values of the case expression, and you did not include a default case item. Incomplete Case Statements may create unintentional latches in the design. For example, consider the following Case Statement:

reg [1:0] sel;
reg [3:0] accidental_latch;
always@(sel) begin
    case(sel)
    2'b00: accidental_latch = 4'b1010;
    2'b01: accidental_latch = 4'b0101;
    2'b10: accidental_latch = 4'b1111;
    // missing Case Item for 2'b11
    endcase
end

            

The Case Statement does not cover the case for sel = 2'b11. When this case occurs, the variable accidental_latch retains its previous value.