ID:10935 Verilog HDL Casex/Casez warning at <location>: casex/casez item expression overlaps with a previous casex/casez item expression

CAUSE: In a casex/casez item at the specified location in a Verilog Design File (.v), you used an expression that overlaps with a previous casex/casez item expression, and at least one expression contains don't care bits. When evaluating such a casex/casez statement, Verilog HDL always executes the first casex/casez item that matches the casex/casez expression. As a result, this overlapping casex/casez item may not execute if the casex/casez expression value falls within the region of overlap. More practically, the overlap forces Quartus Prime Integrated Synthesis to create more complex priority logic to ensure that the previous casex/casez item takes priority. You can override this behavior by adding the parallel_case synthesis attribute to the casex/casez statement or by adding the SystemVerilog unique keyword.

ACTION: No action is required. If you want to eliminate this warning, modify the casex/casez expression to remove the overlap.