ID:10059 Verilog HDL Case Statement warning at <location>: case item expression never matches the case expression because it contains an 'x' or 'z' value

CAUSE: In a Verilog Design File (.v), you used a case item expression that contains a Don't Care (x) or High Impedance (z) value. During simulation, the value of a case item expression must match the value of the case expression exactly. That is, if the value of the case expression has an x in a particular bit position, then the value of the case item expression must also have an x in that position in order to match the case expression. Quartus Prime Integrated Synthesis cannot implement logic to ensure such a match, so it ignored this case item expression when elaborating the Case Statement, which may result in differences between the simulated behavior of the design and the synthesized netlist.

ACTION: If you want to treat x and z as Don't Care values, then replace the Case Statement with a Casex or a Casez Statement. Otherwise, if you intended Quartus Prime Integrated Synthesis to ignore the case item expression, no action is required. You can prevent this warning in the future by removing the case item expression or replacing it with an expression with a binary value.