ID:10034 Output port "<name>" at <location> has no driver

CAUSE: In a Verilog Design File (.v) or a VHDL Design File (.vhd), you declared the specified output port, but you never assigned a value to the output or connected it to an explicit driver, such as an input port on the current entity or an output port on a lower-level instance.

ACTION: If you intended to leave the output port undriven, no action is required. Otherwise, assign a value to the port by using an explicit assignment or by connecting the port to an explicit driver.