ID:10005 Verilog HDL or VHDL warning at <location>: <text>

CAUSE: Quartus Prime Integrated Synthesis generated the specified warning for the specified location in a Verilog Design File (.v) or VHDL Design File (.vhd).

ACTION: Edit the file to avoid problems in the future processing of the design, or to avoid receiving this message in the future. A future version of the Quartus Prime software will provide more detailed information about this warning.