ID:13699 VHDL Signal Declaration warning at <location>: ignored default value for the signal

CAUSE: In a Signal Declaration at the specified location in a VHDL Design File (.vhd), you specified a default value (or power-up state) for the specified signal. However, you also update the signal's value during simulation using a Concurrent or Selected Signal Assignment Statement. Because it cannot generate logic to ensure that a non-constant signal's power-up state matches its default value, Quartus Prime Integrated Synthesis ignored the default value you specified for the signal. As a result, the synthesized design's power-up state may differ from its simulated power-up state.

ACTION: If this behavior is correct, no action is required. To avoid receiving this message in the future, you can remove the default value from the Signal Declaration. If the design requires that a non-constant signal power up to a particular value, rewrite the design so that Quartus Prime Integrated Synthesis infers a register for the signal. You can then specify the power-up state of the register using an explicit reset condition.