ID:13938 VHDL Subprogram Body warning at <location>: value of variable "<name>" used in Subprogram Body expression may depend on variable's default initial value because variable may not be assigned a value in the statements preceding the variable's use in the expression

CAUSE: In a Subprogram Body at the specified location in a Verilog Design File (.v), you used the specified variable in an expression. However, you may not have assigned a value to the variable in every possible path through the statements preceding the variable's use in the expression. In addition, you did not assign an initial value to the variable in its Variable Declaration. As a result, certain conditions may cause the variable in the expression to have a value that depends on the variable's default initial value.

The default initial value for a variable with scalar type T is T'LEFT, or the left-most value in the range of T. The default initial value for a variable with type STD_LOGIC is U, which corresponds to STD_LOGIC'LEFT. The default initial value for a variable with composite type is the assignment of the appropriate default initial value to each of the variable's subelements.

The use of the variable's default initial value may result in unintended design optimizations.

ACTION: To avoid receiving this message in the future, assign a value to the variable prior to its use. In particular, look for If Statements or Case Statements that may create paths where a variable retains its default initial value. You can also assign an appropriate initial value to the variable in its Variable Declaration.