ID:13844 VHDL Signal Declaration warning at <location>: used explicit default value for signal "<name>" because signal was never assigned a value

CAUSE: In a VHDL Design File (.vhd) at the specified location, you declared the specified signal, which you later used in an expression or on the right-hand side (RHS) of an assignment. However, you never assigned a value to the signal with a Concurrent Signal Assignment Statement or Sequential Signal Assignment Statement. As a result, Quartus Prime Integrated Synthesis used the explicit default value you specified in the Signal Declaration for the signal.

ACTION: If you intended to use the explicit default value for the signal, no action is required. Otherwise, assign a value to the signal before using the signal in expressions or on the RHS of assignments.