ID:13798 VHDL Selected Signal Assignment warning at <location>: Selected Signal Assignment choices do not cover all possible values of expression

CAUSE: In a Selected Signal Assignment at the specified location in a VHDL Design File (.vhd), you specified choices for a Selected Signal Assignment expression. However, the choices do not cover all possible values of the expression; as a result, errors may occur during the future processing of the design.

ACTION: Add choices for all possible values of the expression, or add an OTHERS choice, which covers all possible values that are not included in the other Selected Signal Assignment choices.