ID:13796 VHDL Process Statement warning at <location>: signal "<name>" is read inside the Process Statement but isn't in the Process Statement's sensitivity list

CAUSE: In a Process Statement at the specified location in a VHDL Design File (.vhd), you read the value of the specified signal. However, you did not include the signal in the Process Statement's sensitivity list. Although this omission does not affect the logic generated by Quartus Prime Integrated Synthesis, it may cause the design's simulated behavior to differ from the behavior of the synthesized logic. For example, the Process Statement in the following code reads the value of the signal b on the right-hand side of an assignment, but the Process Statement's sensitivity list does not include b:

PROCESS(a)
BEGIN
   o <= a and b;
END PROCESS;

            

During simulation, the Process Statement updates the value of signal o whenever signal a changes value. However, changes to the value of signal b do not trigger the execution of the Process Statement, and thus signal o behaves as a pseudo-latch, that is, it retains its value, whenever signal b alone changes value. Quartus Prime Integrated Synthesis ignores the pseudo-latch behavior implied by the incomplete sensitivity list in the example above. It generates logic as if the sensitivity list were complete, and therefore implements purely combinational logic for signal o.

ACTION: To avoid receiving this message in the future, and to avoid potential mismatches between simulation and the synthesized logic, add the specified signal to the sensitivity list. For example, in the Process Statement above, you would add signal b to the sensitivity list:

PROCESS(a, b)
BEGIN
   o <= a and b;
END PROCESS;