ID:16759 VHDL warning at <location>: formal port or parameter "<string>" has no actual or default value

CAUSE: In a VHDL Design File (.vhd) at the specified location, you used the specified formal parameter. However, you did not assign an actual value to the parameter, and the parameter does not have a default value. For example, in the following code, the function exa has the parameter r, but the Signal Assignment Statement specifies two values for the parameter s and no value for r.

ENTITY example IS
   PORT
   (
      a : IN   BIT;
      b : IN   BIT;
      o : OUT  BIT
   );
END example;

               
ARCHITECTURE a OF example IS
   FUNCTION exa (s,r : BIT) RETURN BIT IS
   BEGIN
      RETURN (s and r);
   END exa;
BEGIN
   o <= exa (s=>a, s=>b);
END a;

The parameter must have a value. In the previous example, the parameter r must have a value. The example for ports is almost the same. Input port i2 is not provided with a value and does not have a default value.

ENTITY t1 IS
	port (	o : out bit );
END;

               
ARCHITECTURE rtl OF t1 IS
COMPONENT t2
	PORT (	i : in bit;
		i2 : in bit;
		o : out bit);
END COMPONENT;
BEGIN
inst : t2 port map ( i=> '1' );
END;

               
ENTITY t2 IS
	PORT (	i : in bit;
		i2 : in bit;
		o : out bit );
END;
ARCHITECTURE rtl OF t2 IS
BEGIN
o <= i and i2;
END;