ID:13849 VHDL Assertion Statement at <location>: assertion is false - report <text> (WARNING)

CAUSE: In an assertion statement at the specified location in a VHDL Design File (.vhd), you used an assertion expression that evaluates to False. The specified text contains the report string associated with the assertion.

ACTION: No action is required. To remove the warning, change your design so that the assertion expression is always true.