ID:13385 Verilog HDL Module Declaration warning at <location>: port "<name>" already exists in the list of ports

CAUSE: In a module declaration at the specified location in a Verilog Design File (.v), you listed the specified port in the module's list of ports. However, the list already contains a listing for the specified port. Quartus Prime Integrated Synthesis will assign an auto-generated name to one of the ports, and you will not be able to connect to this port by name when instantiating this module.

ACTION: No action is required. If you did not intend to list the port more than once, remove any duplicate listings.