ID:13461 Verilog HDL Parameter Declaration warning at <location>: Parameter Declaration in module "<name>" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List

CAUSE: In a Module Declaration at the specified location in a Verilog Design File (.v), you used a Parameter Declaration to declare parameter(s) for the specified module. However, the Module Declaration also has parameter(s) that were declared by a Module Parameter Port List. As a result, the Parameter Declaration implicitly behaves as a Local Parameter Declaration, meaning the parameters it declares are local to the module and cannot be changed during Module Instantiation.

ACTION: If this behavior is correct, no action is required. Otherwise, change the Module Declaration for the specified module so that it declares all its parameters using either a Module Parameter Port List or one or more Parameter Declarations inside the Module Declaration itself.