ID:13478 Verilog HDL warning at <location>: can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead

CAUSE: In a Verilog Design File (.v) at the specified location, you used a Procedural Assignment in an Always Construct whose Event Control (sensitivity list) contains multiple edge triggers. Quartus Prime Integrated Synthesis attempted to infer a register for this assignment, but could not identify a unique clock signal from the list of edge triggers. Instead, Quartus Prime Integrated Synthesis generated combinational logic for this signal assignment. This error usually occurs when the control flow in the Always Construct does not distinguish the clock signal from the asynchronous control signals. For example, the Always Construct in the following code contains a single unconditional Procedural Assignment, but the Event Control contains two edge triggers:

always @(posedge clk or negedge reset)
   begin
      q <= data_in;
   end

            

Because the Always Construct does not contain any conditional logic to differentiate between clk and reset, the Quartus Prime software cannot identify the clock signal.