ID:13434 Verilog HDL unsupported feature warning at <location>: Wait Statement is not supported and is ignored

CAUSE: In a Verilog Design File (.v) at the specified location, you have used a Wait Statement. Although Verilog HDL supports Wait Statements, they are not supported by the Quartus Prime software and are ignored.

ACTION: No action is required. To avoid receiving this message in the future, remove the Wait Statement.